Timeline / ECEN 350 CPU

ECEN 350 CPU

A teaching single-cycle datapath in Verilog: fetch, decode, ALU, register file, and data memory.

What it is

Course lab series (ECEN 350) culminating in a single-cycle processor (SingleCycleProc.v and friends). This portfolio page deliberately omits solution dumps. The diagram below is my own redrawn datapath sketch for the site, not a copy of lab keys.

The GitHub repo ECEN_350_Lab is currently public; that is an academic-integrity risk and should probably be privatized.

My role

Student implementer of the lab RTL and ARM/asm labs on the course Raspberry Pi track.

Tech

Verilog, ARM assembly, C, Makefiles.

Dates

Labs through Spring 2026 (repo activity into March 2026).

Links

No solution links. Course concepts only.

Figures

ecen350-datapath.png — redrawn single-cycle datapath for the site.